C167CS datasheet(263/517 Pages) INFINEON

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C167CS

Derivatives

The General Purpose Timer Units

User’s Manual

10-35

V2.0, 2000-07

When a selected transition at the selected input pin(s) (CAPIN, T3IN, T3EUD) is

detected, the contents of the auxiliary timer T5 are latched into register CAPREL, and

interrupt request flag CRIR is set. With the same event, timer T5 can be cleared to

0000H. This option is controlled by bit T5CLR in register T5CON. If T5CLR = ‘0’, the

contents of timer T5 are not affected by a capture. If T5CLR = ‘1’, timer T5 is cleared

after the current timer value has been latched into register CAPREL.

Note: Bit T5SC only controls whether a capture is performed or not. If T5SC = ‘0’, the

selected trigger event can still be used to clear timer T5 or to generate an interrupt

request. This interrupt is controlled by the CAPREL interrupt control register

CRIC.

GPT2 Capture/Reload Register CAPREL in Reload Mode

This 16-bit register can be used as a reload register for the core timer T6. This mode is

selected by setting bit T6SR = ‘1’ in register T6CON. The event causing a reload in this

mode is an overflow or underflow of the core timer T6.

When timer T6 overflows from FFFFH to 0000H (when counting up) or when it underflows

from 0000H to FFFFH (when counting down), the value stored in register CAPREL is

loaded into timer T6. This will not set the interrupt request flag CRIR associated with the

CAPREL register. However, interrupt request flag T6IR will be set indicating the

overflow/underflow of T6.

Figure 10-23 GPT2 Register CAPREL in Reload Mode

Core Timer T6

Up/Down

Interrupt

Request

T6OE

T6OUT

Input

Clock

MCB02045

T6OTL

T6SR

CAPREL Register

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