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C167CS Datasheet(PDF) 266 Page - Infineon Technologies AG |
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C167CS Datasheet(HTML) 266 Page - Infineon Technologies AG |
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266 / 517 page  C167CS Derivatives The General Purpose Timer Units User’s Manual 10-38 V2.0, 2000-07 10.2.3 Interrupt Control for GPT2 Timers and CAPREL When a timer overflows from FFFFH to 0000H (when counting up), or when it underflows from 0000H to FFFFH (when counting down), its interrupt request flag (T5IR or T6IR) in register TxIC will be set. Whenever a transition according to the selection in bit field CI is detected at pin CAPIN, interrupt request flag CRIR in register CRIC is set. Setting any request flag will cause an interrupt to the respective timer or CAPREL interrupt vector (T5INT, T6INT or CRINT) or trigger a PEC service, if the respective interrupt enable bit (T5IE or T6IE in register TxIC, CRIE in register CRIC) is set. There is an interrupt control register for each of the two timers and for the CAPREL register. Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. T5IC Timer 5 Intr. Ctrl. Reg. SFR (FF66H/B3H) Reset Value: - - 00H 15 14 13 12 11 10 98765 43210 - T5IR T5IE ILVL GLVL - - - - - - - - rwh rw rw RW T6IC Timer 6 Intr. Ctrl. Reg. SFR (FF68H/B4H) Reset Value: - - 00H 15 14 13 12 11 10 98765 43210 - T6IR T6IE ILVL GLVL - - - - - - - - rwh rw rw RW CRIC CAPREL Intr. Ctrl. Reg. SFR (FF6AH/B5H) Reset Value: - - 00H 15 14 13 12 11 10 98765 43210 - CRIR CRIE ILVL GLVL - - - - - - - - rwh rw rw RW |
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