C167CS datasheet(260/517 Pages) INFINEON

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C167CS

Derivatives

The General Purpose Timer Units

User’s Manual

10-32

V2.0, 2000-07

Figure 10-20 Block Diagram of Auxiliary Timer T5 in Counter Mode

The event causing an increment or decrement of the timer can be a positive, a negative,

or both a positive and a negative transition at either the input pin, or at the toggle latch

T6OTL.

Bitfield T5I in control register T5CON selects the triggering transition (see Table 10-14).

Note: Only state transitions of T6OTL which are caused by the overflows/underflows of

T6 will trigger the counter function of T5. Modifications of T6OTL via software will

NOT trigger the counter function of T5.

The maximum input frequency which is allowed in counter mode is

fCPU / 8. To ensure

that a transition of the count input signal which is applied to T5IN is correctly recognized,

its level should be held high or low for at least 4

fCPU cycles before it changes.

Table 10-14 GPT2 Auxiliary Timer (Counter Mode) Input Edge Selection

T5I

Triggering Edge for Counter Increment/Decrement

X 0 0

None. Counter T5 is disabled

0 0 1

Positive transition (rising edge) on T5IN

0 1 0

Negative transition (falling edge) on T5IN

0 1 1

Any transition (rising or falling edge) on T5IN

1 0 1

Positive transition (rising edge) of output toggle latch T6OTL

1 1 0

Negative transition (falling edge) of output toggle latch T6OTL

1 1 1

Any transition (rising or falling edge) of output toggle latch T6OTL

Auxiliary Timer Tx

Interrupt

Request

TxR

XOR

MUX

TxEUD

TxUDE

MCB02221

TxUD

Txl

TxIN

Edge

Select

Up/

Down

x = 5

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