C167CS datasheet(257/517 Pages) INFINEON

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C167CS

Derivatives

The General Purpose Timer Units

User’s Manual

10-29

V2.0, 2000-07

Timer 6 in Counter Mode

Counter mode for the core timer T6 is selected by setting bit field T6M in register T6CON

to ‘001B’. In counter mode timer T6 is clocked by a transition at the external input pin

T6IN, which is an alternate function of P5.12. The event causing an increment or

decrement of the timer can be a positive, a negative, or both a positive and a negative

transition at this pin. Bit field T6I in control register T6CON selects the triggering

transition (see Table 10-13).

Figure 10-19 Block Diagram of Core Timer T6 in Counter Mode

The maximum input frequency which is allowed in counter mode is

fCPU / 8. To ensure

that a transition of the count input signal which is applied to T6IN is correctly recognized,

its level should be held high or low for at least 4

fCPU cycles before it changes.

Table 10-13 GPT2 Core Timer T6 (Counter Mode) Input Edge Selection

T6I

Triggering Edge for Counter Increment/Decrement

0 0 0

None. Counter T6 is disabled

0 0 1

Positive transition (rising edge) on T6IN

0 1 0

Negative transition (falling edge) on T6IN

0 1 1

Any transition (rising or falling edge) on T6IN

1 X X

Reserved. Do not use this combination

Core Timer Tx

TxR

XOR

MUX

Up/

Down

TxEUD

TxUDE

MCB02030

TxUD

Txl

TxIN

Edge

Select

TxOTL

TxOE

TxOUT

Interrupt

Request

T6IN = P5.12

T6EUD = P5.10

T6OUT = P3.1

x = 6

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