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C167CS Datasheet(PDF) 258 Page - Infineon Technologies AG |
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C167CS Datasheet(HTML) 258 Page - Infineon Technologies AG |
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258 / 517 page ![]() C167CS Derivatives The General Purpose Timer Units User’s Manual 10-30 V2.0, 2000-07 10.2.2 GPT2 Auxiliary Timer T5 The auxiliary timer T5 can be configured for timer, gated timer or counter mode with the same options for the timer frequencies and the count signal as the core timer T6. In addition the auxiliary timer can be concatenated with the core timer (operation in counter mode). Its contents may be captured to register CAPREL upon a selectable trigger. The individual configuration for timer T5 is determined by its bitaddressable control register T5CON. Note that functions which are present in both timers of block GPT2 are controlled in the same bit positions and in the same manner in each of the specific control registers. Note: The auxiliary timer has no output toggle latch and no alternate output function. T5CON Timer 5 Control Register SFR (FF46H/A3H) Reset Value: 0000H 15 14 13 12 11 10 9876 543210 T5 SC T5 CLR CI - CT3 - T5 UDE T5 UD T5R T5M T5I rw rw rw - rw - rw rw rw rw rw Bit Function T5I Timer 5 Input Selection Depends on the Operating Mode, see respective sections. T5M Timer 5 Mode Control (Basic Operating Mode) 000: Timer Mode 001: Counter Mode 010: Gated Timer with Gate active low 011: Gated Timer with Gate active high 1XX: Reserved. Do not use this combination. T5R Timer 5 Run Bit 0: Timer / Counter 5 stops 1: Timer / Counter 5 runs T5UD Timer 5 Up / Down Control1) T5UDE Timer 5 External Up/Down Enable1) CT3 Timer 3 Capture Trigger Enable 0: Capture trigger from pin CAPIN 1: Capture trigger from T3 input pins |
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