C167CS datasheet(256/517 Pages) INFINEON

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C167CS

Derivatives

The General Purpose Timer Units

User’s Manual

10-28

V2.0, 2000-07

Timer 6 in Gated Timer Mode

Gated timer mode for the core timer T6 is selected by setting bit field T6M in register

T6CON to ‘010B’ or ‘011B’. Bit T6M.0 (T6CON.3) selects the active level of the gate

input. In gated timer mode the same options for the input frequency as for the timer mode

are available. However, the input clock to the timer in this mode is gated by the external

input pin T6IN (Timer T6 External Input).

Figure 10-18 Block Diagram of Core Timer T6 in Gated Timer Mode

If T6M.0 = ‘0’, the timer is enabled when T6IN shows a low level. A high level at this pin

stops the timer. If T6M.0 = ‘1’, pin T6IN must have a high level in order to enable the

timer. In addition, the timer can be turned on or off by software using bit T6R. The timer

will only run, if T6R = ‘1’ and the gate is active. It will stop, if either T6R = ‘0’ or the gate

is inactive.

Note: A transition of the gate signal at pin T6IN does not cause an interrupt request.

MUX

Core Timer Tx

TxOTL

Interrupt

Request

TxOE

TxOUT

TxR

XOR

MUX

Up/

Down

TxEUD

TxUDE

MCB02029

TxUD

2n : 1

TxI

CPU

TxM

TxIN

T6IN = P5.12

T6EUD = P5.10

x = 6

T6OUT = P3.1

n = 2 … 9

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