C167CS datasheet(273/517 Pages) INFINEON

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C167CS

Derivatives

The Asynchronous/Synchronous Serial Interface

User’s Manual

11-7

V2.0, 2000-07

Asynchronous transmission begins at the next overflow of the divide-by-16 counter

(see Figure 11-4), provided that S0R is set and data has been loaded into S0TBUF. The

transmitted data frame consists of three basic elements:

• the start bit

• the data field (8 or 9 bits, LSB first, including a parity bit, if selected)

• the delimiter (1 or 2 stop bits)

Data transmission is double buffered. When the transmitter is idle, the transmit data

loaded into S0TBUF is immediately moved to the transmit shift register thus freeing

S0TBUF for the next data to be sent. This is indicated by the transmit buffer interrupt

request flag S0TBIR being set. S0TBUF may now be loaded with the next data, while

transmission of the previous one is still going on.

The transmit interrupt request flag S0TIR will be set before the last bit of a frame is

transmitted, i.e. before the first or the second stop bit is shifted out of the transmit shift

The transmitter output pin TXD0 must be configured for alternate data output, i.e. the

respective port output latch and the direction latch must be ‘1’.

Asynchronous reception is initiated by a falling edge (1-to-0 transition) on pin RXD0,

provided that bits S0R and S0REN are set. The receive data input pin RXD0 is sampled

at 16 times the rate of the selected baud rate. A majority decision of the 7th, 8th and 9th

sample determines the effective bit value. This avoids erroneous results that may be

caused by noise.

If the detected value is not a ‘0’ when the start bit is sampled, the receive circuit is reset

and waits for the next 1-to-0 transition at pin RXD0. If the start bit proves valid, the

receive circuit continues sampling and shifts the incoming data frame into the receive

shift register.

When the last stop bit has been received, the content of the receive shift register is

transferred to the receive data buffer register S0RBUF. Simultaneously, the receive

interrupt request flag S0RIR is set after the 9th sample in the last stop bit time slot (as

programmed), regardless whether valid stop bits have been received or not. The receive

circuit then waits for the next start bit (1-to-0 transition) at the receive data input pin.

The receiver input pin RXD0 must be configured for input, i.e. the respective direction

latch must be ‘0’.

Asynchronous reception is stopped by clearing bit S0REN. A currently received frame is

completed including the generation of the receive interrupt request and an error interrupt

request, if appropriate. Start bits that follow this frame will not be recognized.

Note: In wake-up mode received frames are only transferred to the receive buffer

request will be activated and no data will be transferred.

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