C167CS datasheet(275/517 Pages) INFINEON

275 / 517 page

C167CS

Derivatives

The Asynchronous/Synchronous Serial Interface

User’s Manual

11-9

V2.0, 2000-07

Synchronous transmission begins within 4 state times after data has been loaded into

S0TBUF, provided that S0R is set and S0REN = ‘0’ (half-duplex, no reception). Data

transmission is double buffered. When the transmitter is idle, the transmit data loaded

into S0TBUF is immediately moved to the transmit shift register thus freeing S0TBUF for

the next data to be sent. This is indicated by the transmit buffer interrupt request flag

S0TBIR being set. S0TBUF may now be loaded with the next data, while transmission

of the previous one is still going on. The data bits are transmitted synchronous with the

shift clock. After the bit time for the 8th data bit, both pins TXD0 and RXD0 will go high,

the transmit interrupt request flag S0TIR is set, and serial data transmission stops.

Pin TXD0 must be configured for alternate data output, i.e. the respective port output

latch and the direction latch must be ‘1’, in order to provide the shift clock. Pin RXD0

must also be configured for output (output/direction latch = ‘1’) during transmission.

Synchronous reception is initiated by setting bit S0REN = ‘1’. If bit S0R = ‘1’, the data

applied at pin RXD0 are clocked into the receive shift register synchronous to the clock

which is output at pin TXD0. After the 8th bit has been shifted in, the content of the

receive shift register is transferred to the receive data buffer S0RBUF, the receive

interrupt request flag S0RIR is set, the receiver enable bit S0REN is reset, and serial

data reception stops.

Pin TXD0 must be configured for alternate data output, i.e. the respective port output

latch and the direction latch must be ‘1’, in order to provide the shift clock. Pin RXD0

must be configured as alternate data input, i.e. the respective direction latch must be ‘0’.

Synchronous reception is stopped by clearing bit S0REN. A currently received byte is

completed including the generation of the receive interrupt request and an error interrupt

request, if appropriate. Writing to the transmit buffer register while a reception is in

progress has no effect on reception and will not start a transmission.

If a previously received byte has not been read out of the receive buffer register at the

time the reception of the next byte is complete, both the error interrupt request flag

S0EIR and the overrun error status flag S0OE will be set, provided the overrun check

has been enabled by bit S0OEN.

C167CS Datasheet(PDF) 275 Page - Infineon Technologies AG