C167CS datasheet(272/517 Pages) INFINEON

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C167CS

Derivatives

The Asynchronous/Synchronous Serial Interface

User’s Manual

11-6

V2.0, 2000-07

S0PE will be set along with the error interrupt request flag, if a wrong parity bit is

received. The parity bit itself will be stored in bit S0RBUF.7.

Figure 11-3

Asynchronous 8-bit Data Frames

9-bit data frames either consist of 9 data bits D8 … D0 (S0M = ‘100B’), of 8 data bits

D7 … D0 plus an automatically generated parity bit (S0M = ‘111B’) or of 8 data bits

D7 … D0 plus wake-up bit (S0M = ‘101B’). Parity may be odd or even, depending on bit

S0ODD in register S0CON. An even parity bit will be set, if the modulo-2-sum of the

8 data bits is ‘1’. An odd parity bit will be cleared in this case. Parity checking is enabled

via bit S0PEN (always OFF in 9-bit data and wake-up mode). The parity error flag S0PE

will be set along with the error interrupt request flag, if a wrong parity bit is received. The

parity bit itself will be stored in bit S0RBUF.8.

In wake-up mode received frames are only transferred to the receive buffer register, if

the 9th bit (the wake-up bit) is ‘1’. If this bit is ‘0’, no receive interrupt request will be

activated and no data will be transferred.

This feature may be used to control communication in multi-processor system:

When the master processor wants to transmit a block of data to one of several slaves, it

first sends out an address byte which identifies the target slave. An address byte differs

from a data byte in that the additional 9th bit is a ‘1’ for an address byte and a ‘0’ for a

data byte, so no slave will be interrupted by a data ‘byte’. An address ‘byte’ will interrupt

all slaves (operating in 8-bit data + wake-up bit mode), so each slave can examine the

8 LSBs of the received character (the address). The addressed slave will switch to 9-bit

data mode (e.g. by clearing bit S0M.0), which enables it to also receive the data bytes

that will be coming (having the wake-up bit cleared). The slaves that were not being

addressed remain in 8-bit data + wake-up bit mode, ignoring the following data bytes.

Figure 11-4

Asynchronous 9-bit Data Frames

D7 /

Parity

MCT04377

(LSB)

Start

Bit

(1st)

Stop

Bit

2nd

Stop

Bit

MCT04378

(LSB)

Start

Bit

(1st)

Stop

Bit

2nd

Stop

Bit

9th

Bit

Data Bit D8

Parity

Wake-up Bit

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