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C167CS Datasheet(PDF) 354 Page - Infineon Technologies AG |
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C167CS Datasheet(HTML) 354 Page - Infineon Technologies AG |
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354 / 517 page  C167CS Derivatives The Pulse Width Modulation Module User’s Manual 17-13 V2.0, 2000-07 PWM Control Register PWMCON1 Register PWMCON1 controls the operating modes and the outputs of the four PWM channels. The basic operating mode for each channel (standard = edge aligned, or symmetrical = center aligned PWM mode) is selected by the mode bits PMx. Burst mode (channels 0 and 1) and single shot mode (channel 2 or 3) are selected by separate control bits. The output signal of each PWM channel is individually enabled by bit PENx. If the output is not enabled the respective pin can be used for general purpose IO and the PWM channel can only be used to generate an interrupt request. PWMCON1 PWM Control Register 1 SFR (FF32H/99H) Reset Value: 0000H 15 14 13 12 11 10 9876 543210 PS3 PS2 - PB 01 ---- PM3 PM2 PM1 PM0 PEN 3 PEN 2 PEN 1 PEN 0 rw rw - rw - - - - rw rw rw rw rw rw rw rw Bit Function PENx PWM Channel x Output Enable Bit 0: Channel x output signal disabled, generate interrupt only 1: Channel x output signal enabled PMx PWM Channel x Mode Control Bit 0: Channel x operates in mode 0, i.e. edge aligned PWM 1: Channel x operates in mode 1, i.e. center aligned PWM PB01 PWM Channel 0/1 Burst Mode Control Bit 0: Channel 0 and channel 1 work independently in their respective standard mode 1: Outputs of channels 0 and 1 are ANDed to POUT0 in burst mode PSx PWM Channel x Single Shot Mode Control Bit 0: Channel x works in respective standard mode 1: Channel x operates in single shot mode |
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