C167CS datasheet(355/517 Pages) INFINEON

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C167CS

Derivatives

The Pulse Width Modulation Module

User’s Manual

17-14

V2.0, 2000-07

17.3

Interrupt Request Generation

Each of the four channels of the PWM module can generate an individual interrupt

request. Each of these “channel interrupts” can activate the common “module interrupt”,

which actually interrupts the CPU. This common module interrupt is controlled by the

PWM Module Interrupt Control register PWMIC. The interrupt service routine can

determine the active channel interrupt(s) from the channel specific interrupt request flags

PIRx in register PWMCON0. The interrupt request flag PIRx of a channel is set at the

beginning of a new PWM cycle, i.e. upon latching the shadow registers (LSR). This

indicates that registers PPx and PWx are now ready to receive a new value. If a channel

interrupt is enabled via its respective PIEx bit, also the common interrupt request flag

PWMIR in register PWMIC is set, provided that it is enabled via the common interrupt

enable bit PWMIE.

Note: The channel interrupt request flags (PIRx in register PWMCON0) are not

automatically cleared by hardware upon entry into the interrupt service routine, so

they must be cleared via software. The module interrupt request flag PWMIR is

cleared by hardware upon entry into the service routine, regardless of how many

channel interrupts were active. However, it will be set again if during execution of

the service routine a new channel interrupt request is generated.

Note: Please refer to the general Interrupt Control Register description for an

explanation of the control fields.

PWMIC

PWM Intr. Ctrl. Reg.

ESFR (F17EH/BFH)

Reset Value: - - 00H

98765

43210

PWM

ILVL

GLVL

rwh

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