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LX256VCF2085 Datasheet(PDF) 33 Page - Lattice Semiconductor |
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LX256VCF2085 Datasheet(HTML) 33 Page - Lattice Semiconductor |
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33 / 72 page  Lattice Semiconductor ispGDX2 Family Data Sheet 33 ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters 1 Over Recommended Operating Conditions Parameter Description -3 -32 -35 -5 Units Min. Max. Min. Max. Min. Max. Min. Max. Input/Output Delays tBUF Output Buffer Delay — 0.80 — 0.80 — 0.80 — 1.14 ns tCLK_IN Global Clock Input Delay — 1.00 — 1.00 — 1.00 — 1.67 ns tCLKEN_IN Global Clock Enable Input Delay — 1.80 — 1.80 — 1.80 — 3.00 ns tDIS Output Disable Delay — 1.80 — 1.80 — 2.50 — 4.17 ns tEN Output Enable Delay — 1.50 — 1.80 — 2.50 — 4.17 ns tGOE_IN Global Output Enable Path Delay — 2.00 — 2.00 — 2.00 — 3.33 ns tIN Input Pin Delay — 0.40 — 0.40 — 0.40 — 0.57 ns tSEL_IN Global MUX Select Input Delay — 1.60 — 1.60 — 1.60 — 2.29 ns tSR_IN Global Set/Reset Path Delay — 2.00 — 2.70 — 2.70 — 4.50 ns tTOE_IN Test Output Enable Path Delay — 3.70 — 3.70 — 3.70 — 6.17 ns Shift Register and MUX Delays tIPAC Input Path Adjacent I/O Cell Delay (Shift Register) — 0.80 — 0.80 — 0.80 — 1.33 ns tOPAC Output Path Adjacent I/O Cell Delay (Shift Register) — 1.30 — 1.30 — 1.30 — 2.17 ns tMUXPD MUX Data Path Delay — 0.90 — 0.90 — 0.90 — 1.29 ns tMUXSEL MUX Select Path Delay — 0.40 — 0.40 — 0.40 — 0.57 ns AND Arrays and Routing Delays tFIFODATAOUT FIFO Output to I/O Block Delay — 0.00 — 0.00 — 0.00 — 0.00 ns tGCLK Clock Tree Delay — 0.40 — 0.40 — 0.40 — 0.67 ns tHSIFIFOFLAG HSI/FIFO Flag to I/O Block Delay — 0.00 — 0.00 — 0.00 — 0.00 ns tHSIOUT HSI Output to I/O Cell Block Delay — 0.00 — 0.00 — 0.00 — 0.00 ns tHSISSCLKOUT HSI Source Synchronous Clock to I/O Cell Block Delay — 0.00 — 0.00 — 0.00 — 0.00 ns tPLL_DELAY PLL Delay Increment — 0.33 — 0.33 — 0.33 — 0.33 ns tPTCLK Clock AND Array Delay — 2.20 — 2.20 — 2.20 — 3.67 ns tPTCLKEN Clock Enable AND Array Delay — 2.10 — 2.10 — 2.10 — 3.50 ns tPTOE OE AND Array Delay — 2.40 — 2.40 — 2.40 — 4.00 ns tPTSEL Select AND Array Delay — 1.70 — 1.70 — 1.70 — 2.83 ns tPTSR Set/Reset AND Array Delay — 1.40 — 1.40 — 2.70 — 4.50 ns tROUTEGRP Global Routing Pool Delay — 0.90 — 0.90 — 0.90 — 1.29 ns Register/Latch Delays, Output Paths tOPASROi Asynchronous Set/Reset to Output — 2.50 — 2.50 — 2.50 — 4.17 ns tOPASRRi Asynchronous Set/Reset Recovery — 2.50 — 2.50 — 2.50 — 4.17 ns tOPBYPASS Register/Latch Bypass Delay — 0.00 — 0.20 — 0.50 — 0.71 ns tOPCEHi Register Clock Enable Hold Time 1.30 — 1.30 — 1.30 — 2.17 — ns tOPCESi Register Clock Enable Setup Time (Global Clock Enable) 1.10 — 1.10 — 1.10 — 1.83 — ns tOPCESi_PT Register Clock Enable Setup Time (Product Term Clock Enable) 1.00 — 1.00 — 2.10 — 3.50 — ns tOPCOi Register Clock to Output Delay — 0.70 — 0.90 — 1.00 — 1.67 ns tOPHi Register Hold Time 0.80 — 0.80 — 0.80 — 1.33 — ns |
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