LX256VCF2085 datasheet(29/72 Pages) LATTICE

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Lattice Semiconductor

ispGDX2 Family Data Sheet

Timing Model

The task of determining the timing through the ispGDX2 family is relatively simple. The timing model provided in

Figure 18 shows the speciﬁc delay paths. Once the implementation of a given function is determined either con-

ceptually or from the software report ﬁle, the delay path of the function can easily be determined from the timing

model. The Lattice design tools report the timing delays based on the same timing model for a particular design.

Note that the internal timing parameters are given for reference only, and are not tested. The external timing param-

eters are tested and guaranteed for every device.

Figure 18. ispGDX2 Timing Model Diagram (I/O Cell)

GSR

INDIO

OE Reg.

S/R

OPBYPASS

IPBYPASS

ROUTEGRP

to GRP

from GRP

PTSEL

from GRP

from Adjacent

Cells (Output)

PTCLKEN

PTCLK

from GRP

OEBYPASS

PTSR

from GRP

Output

Delays

BUF

DIS

IOO

OUT

PTOE

TOE path

GOE path

from GRP

to Adjacent Cells

(Input)

OPAC

Italicized parameters are optional.

Model Version 1.6.7

TOE/

GOE

GSEL

MUXPD

MUXSEL

IOI

TOE_IN

GOE_IN

SR_IN

IOI

SEL_IN

IOI

to sysHSI/FIFO

(SIN, Control, DIN, I/O Reset, SSCLKIN)

to sysHSI

(TXD)

to Adjacent Cells

(Output)

to FIFO

(REN)

to FIFO

(RCLK)

CLK_IN

IOI

CLKEN_IN

GCLK/

GCLKEN

GCLK

PLL_DELAY

PLL_SEC_DELAY

to sysHSI

(REFCLK)

to sysHSI/FIFO

(Global Reset)

from sysHSI

(SSCLKOUT)

HSISSCLKOUT

to FIFO

(WCLK)

to FIFO

(WE)

from sysHSI/FIFO

(Flags)

HSIFIFOFLAG

from sysHSI

(SOUT)

HSISOUT

from Adjacent Cells

(Input)

IPAC

from FIFO

(DOUT)

FIFODATAOUT

from sysHSI

(RECCLK, SYDT)

HSIOUT

from PLL

(PLL Output)

PLLOUT

Output Reg.

Input Reg.

S/R

LX256VCF2085 Datasheet(PDF) 29 Page - Lattice Semiconductor

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