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LX256VCF2085 Datasheet(PDF) 40 Page - Lattice Semiconductor |
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LX256VCF2085 Datasheet(HTML) 40 Page - Lattice Semiconductor |
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40 / 72 page  Lattice Semiconductor ispGDX2 Family Data Sheet 40 LOCKIN Time REFCLK and SS_CLKIN Timing Serializer Timing 2 Symbol Description Mode Condition Min. Max. Units tSCLOCK CSPLL Lock Time All After input is stabilized 25 μS tCDRLOCK CDRPLL Lock-in Time SS With SS mode sync pattern 1024 tRCP 1 10B12B With 10B12B sync pattern 1024 tRCP 8B10B With 8B10B idle pattern 960 tRCP tSYNC SyncPat Length SS 1200 tRCP tCAL CAL Duration SS 1100 tRCP tSUSYNC SyncPat Set-up Time to CAL SS 50 tRCP tHDSYNC SyncPat Hold Time from CAL SS 50 tRCP 1. REFCLK clock period. Symbol Description Mode Condition Min. Max. Units tDREFCLK Frequency Deviation Between TX REFCLK and CDRX REFCLK on One Link 8B10B/ 10B12B -100 100 ppm tJPPREFCLK REFCLK, SS_CLKIN Peak-to-Peak Period Jitter All Random Jitter 0.01 UIPP tPWREFCLK REFCLK, SS_CLKIN Pulse Width, (80% to 80% or 20% to 20%). All 1 ns tRFREFCLK REFCLK, SS_CLKIN Rise/Fall Time (20% to 80% or 80% to 20%) All 2 ns Symbol Description Mode Condition Min. Max. Units tJPPSOUT SOUT Peak-to-Peak Output Data Jitter All fCLK with no jitter 0.25 UIPP tJPP8B10B SOUT Peak-to-Peak Random Jitter 8B10B 800 Mbps w/K28.7- 130 ps SOUT Peak-to-Peak Deterministic Jitter 8B10B 800 Mbps w/K28.5+ 160 ps tRFSOUT SOUT Output Data Rise/Fall Time (20%, 80%) LVDS 700 ps BLVDS 900 ps tCOSOUT REFCLK to SOUT Delay SS/8B10B 2Bt 1 + 2 2Bt 1 +10 ns 10B12B 1Bt 1 + 2 1Bt 1 +10 ns tSKTX Skew of SOUT with Respect to SS_CLKOUT SS 250 ps tCKOSOUT SS_CLKOUT to bit0 of SOUT SS 2Bt 1 - tSKTX 2Bt1 + tSKTX ns tHSITXDDATAS TXD Data Setup Time All Note 3 1.5 ns tHSITXDDATAH TXD Data Hold Time All Note 3 1.0 ns 1. Bt: Bit Time Period. High Speed Serial Bit Time. 2. The SIN and SOUT jitter specifications listed above are under the condition that the clock tree that drives the REFCLK to sysHSI Block is in sysCLOCK PLL BYPASS mode. 3. Internal timing for reference only. |
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