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LX256VCF2085 Datasheet(PDF) 34 Page - Lattice Semiconductor |
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LX256VCF2085 Datasheet(HTML) 34 Page - Lattice Semiconductor |
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34 / 72 page  Lattice Semiconductor ispGDX2 Family Data Sheet 34 tOPLGOi Latch Gate to Output Delay — 1.00 — 1.00 — 1.00 — 1.67 ns tOPLHi Latch Hold Time 0.80 — 0.80 — 0.80 — 1.33 — ns tOPLPDi Latch Propagation Delay (Transparent Mode) — 0.30 — 0.30 — 0.30 — 0.50 ns tOPLSi Latch Setup Time (Global Gate) 1.20 — 1.20 — 1.20 — 2.00 — ns tOPLSi_PT Latch Setup Time (Product Term Gate) 1.00 — 1.00 — 1.00 — 1.67 — ns tOPSi Register Setup Time (Global Clock) 1.20 — 1.20 — 1.20 — 2.00 — ns tOPSi_PT Register Setup Time (Product Term Clock) 1.00 — 1.00 — 1.00 — 1.67 — ns tOPSRPWi Asynchronous Set/Reset Pulse Width — 2.50 — 2.50 — 2.50 — 4.17 ns Register/Latch Delays, Input Paths tIPASROi Asynchronous Set/Reset to Output — 1.00 — 1.00 — 1.70 — 2.83 ns tIPASRRi Asynchronous Set/Reset Recovery — 2.50 — 2.50 — 2.50 — 4.17 ns tIPBYPASS Register/Latch Bypass Delay — 0.00 — 0.00 — 0.00 — 0.00 ns tIPCEHi Register Clock Enable Hold Time 1.30 — 1.30 — 1.30 — 2.17 — ns tIPCESi Register Clock Enable Setup Time (Global Clock Enable) 1.10 — 1.10 — 1.10 — 1.83 — ns tIPCESi_PT Register Clock Enable Setup Time (Product Term Clock Enable) 1.10 — 1.10 — 1.10 — 1.83 — ns tIPCOi Register Clock to Output Delay — 0.80 — 1.00 — 1.00 — 1.67 ns tIPHi Register Hold Time 0.00 — 0.00 — 0.00 — 0.00 — ns tIPLGOi Latch Gate to Output Delay — 1.00 — 1.00 — 1.00 — 1.67 ns tIPLHi Latch Hold Time 0.00 — 0.00 — 0.00 — 0.00 — ns tIPLPDi Latch Propagation Delay (Transparent Mode) — 0.30 — 0.30 — 0.30 — 0.50 ns tIPLSi Latch Setup Time (Global Term) 1.50 — 1.50 — 1.50 — 2.50 — ns tIPLSi_PT Latch Setup Time (Product Term Gate) 1.50 — 1.50 — 1.50 — 2.50 — ns tIPSi Register Setup Time (Global Clock) 1.50 — 1.50 — 1.50 — 2.50 — ns tIPSi_PT Register Setup Time (Product Term Clock) 1.50 — 1.50 — 1.50 — 2.50 — ns tIPSRPWi Asynchronous Set/Reset Pulse Width — 2.50 — 2.50 — 2.50 — 4.17 ns OE Paths tOEASROi Asynchronous Set/Reset to Output — 2.50 — 2.50 — 2.50 — 4.17 ns tOEASRRi Asynchronous Set/Reset Recovery — 2.50 — 2.50 — 2.50 — 4.17 ns tOEBYPASS Register/Latch Bypass Delay — 0.00 — 0.00 — 0.00 — 0.00 ns tOECEHi Register Clock Enable Hold Time 1.30 — 1.30 — 0.80 — 1.33 — ns tOECESi Register Clock Enable Setup Time (Global Clock Enable) 1.20 — 1.20 — 1.20 — 2.00 — ns tOECESi_PT Register Clock Enable Setup Time (Product Term Clock Enable) 1.50 — 1.50 — 2.10 — 3.50 — ns tOECOi Register Clock to Output Delay — 1.30 — 1.30 — 1.60 — 2.67 ns tOEHi Register Hold Time 0.40 — 0.40 — 0.40 — 0.67 — ns tOELGOi Latch Gate to Output Delay — 1.60 — 1.60 — 1.60 — 2.67 ns tOELHi Latch Hold Time 0.40 — 0.40 — 0.40 — 0.67 — ns tOELPDi Latch Propagation Delay (Transparent Mode) — 0.30 — 0.30 — 0.30 — 0.50 ns ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters 1 (Continued) Over Recommended Operating Conditions Parameter Description -3 -32 -35 -5 Units Min. Max. Min. Max. Min. Max. Min. Max. |
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