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LX256VCF2085 Datasheet(PDF) 59 Page - Lattice Semiconductor |
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LX256VCF2085 Datasheet(HTML) 59 Page - Lattice Semiconductor |
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59 / 72 page  Lattice Semiconductor ispGDX2 Family Data Sheet 59 GND 6 - - - - - GND BK6_IO12 6 54N 3A 12 - HSI3A_RXD2/TXD2 FIFO3A_DIN2/DOUT2 L3 BK6_IO13 6 54P 3A 13 Note 4 HSI3A_RXD1/TXD1 FIFO3A_DIN1/DOUT1 N2 BK6_IO14 6 55N 3A 14 - HSI3A_RXD0/TXD0 FIFO3A_DIN0/DOUT0 P1 BK6_IO15 / VREF6 6 55P 3A 15 - HSI3A_SYDT 5 FIFO3A_ FULL P2 TDI - - - - - - N3 GOE0 - - - - - - T8 GND 7 - - - - - GND BK7_IO0 / VREF7 7 56P 3B 0 FIFO3B_STRDb 6 -- T2 BK7_IO1 7 56N 3B 1 HSI3B_CDRRSTb HSI3B_RECCLK FIFO3B_FIFORSTb R3 BK7_IO2 7 57P 3B 2 HSI3B_SYDT 5 HSI3B_RXD9/TXD9 FIFO3B_DIN9/DOUT9 P4 BK7_IO3 7 57N 3B 3 - HSI3B_RXD8/TXD8 FIFO3B_DIN8/DOUT8 T3 BK7_IO4 7 58P 3B 4 HSI3B_SOUTP HSI3B_RXD7/TXD7 FIFO3B_DIN7/DOUT7 N5 BK7_IO5 7 58N 3B 5 HSI3B_SOUTN HSI3B_RXD6/TXD6 FIFO3B_DIN6/DOUT6 P5 BK7_IO6 7 59P 3B 6 - HSI3B_RXD5/TXD5 FIFO3B_DIN5/DOUT5 R4 BK7_IO7 7 59N 3B 7 Note 4 HSI3B_RXD4/TXD4 FIFO3B_DIN4/DOUT4 T4 BK7_IO8 7 60P 3B 8 - HSI3B_RXD3/TXD3 FIFO3B_DIN3/DOUT3 R5 BK7_IO9 7 60N 3B 9 - HSI3B_RXD2/TXD2 FIFO3B_DIN2/DOUT2 P6 BK7_IO10 7 61P 3B 10 HSI3B_SINP HSI3B_RXD1/TXD1 FIFO3B_DIN1/DOUT1 N7 BK7_IO11 7 61N 3B 11 HSI3B_SINN HSI3B_RXD0/TXD0 FIFO3B_DIN0/DOUT0 P7 GND 7 - - - - - GND BK7_IO12 7 62P 3B 12 - HSI3B_SYDT 5 FIFO3B_ EMPTY R6 BK7_IO13 7 62N 3B 13 - - - T6 BK7_IO14 7 63P 3B 14 - - - R7 BK7_IO15 7 63N 3B 15 - - FIFO3B_FULL T7 1. The signals in this column route to/from the assigned pins of the associated I/O cell. 2. The signals in this column use the I/O cell. If a receiver signal is present in the I/O cell, the associated pin is available for output only. When transmit data (TXD) is present in the cell, the associated pin is available for input only. 3. The DOUT outputs are routed to GRP through the input register of the cell and the DIN inputs are routed direct from the associated pins in FIFO only mode. In SERDES with FIFO mode, the FULL and EMPTY flags are routed to the associated pins through the output MUX and the pins. 4. If the Source Synchronous Receiver is used in the HSI Block, this pin is unavailable for another use and must be left unconnected. 5. The SYDT signal has two routing options. If direct output through the dedicated pin is used, the I/O cell (the whole HSI Block) is not avail- able for transmitter. The SYDT in the I/O Cell column is routed to the GRP through the input register of the cell and frees the I/O cell for transmitter. 6. FIFO_STRDb flag output is used in SERDES with FIFO Mode only. 7. sysHSI Source Synchronous Receive Mode is not available for channel 1A. ispGDX2-128 Logic Signal Connections (Continued) Signal Name sysIO Bank LVDS Pair/Polarity GDX Block MRB SERDES Mode I/O Pin 1 SERDES Mode I/O Cell 2 FIFO Mode I/O Cell/Pin 3 208 fpBGA |
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