LX256VCF2085 datasheet(14/72 Pages) LATTICE

14 / 72 page

Lattice Semiconductor

ispGDX2 Family Data Sheet

Operating Modes

All the GDX Blocks in the ispGDX2 family can be programmed in four modes: Basic, FIFO only, SERDES only, and

FIFO with SERDES mode. In basic mode, the SERDES and FIFO are disabled and the MUX output of the MRB

connects to the output register. Inputs are connected to the GRP via the MRB.

Figure 11 shows the four different operating modes. Precise detail of the FIFO and SERDES connections is pro-

vided in their respective sections.

Figure 11. Four Operating Modes of ispGDX2 Devices

FIFO Operations

Each GDX Block is associated with a 10-bit wide and 15-word deep (10x15) RAM. This RAM, combined with two

address counters and two comparators, is used to implement a FIFO as a “circular queue”. The FIFO has separate

clocks, the Read Clock (RCLK) and Write Clock (WCLK), for asynchronous operation. The FIFO has three addi-

tional control signals Write Enable, Read Enable and FIFO Reset. Three ﬂags show the status of the FIFO: Empty,

Full and Start Read. Each FIFO receives the global Power-on Reset and Reset signals. Figure 12 shows the con-

nections to the FIFO.

GDX

Block

sysIO

Bank

Basic

Mode

GRP

SERDES

FIFO

GDX

Block

sysIO

Bank

FIFO

Mode

GRP

SERDES

FIFO

GDX

Block

sysIO

Bank

SERDES

Mode

(FIFO in

Flow-through

Mode)

GRP

SERDES

FIFO*

*FIFO held in RESET for SERDES-only mode.

GDX

Block

sysIO

Bank

SERDES

and

FIFO Mode GRP

SERDES

FIFO

LX256VCF2085 Datasheet(PDF) 14 Page - Lattice Semiconductor

LX256VCF2085 Datasheet(HTML) 14 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL