LX256VCF2085 datasheet(35/72 Pages) LATTICE

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Lattice Semiconductor

ispGDX2 Family Data Sheet

tOELSi

Latch Setup Time (Global Gate)

1.40

—

1.40

—

1.40

—

2.33

—

tOELSi_PT

Latch Setup Time (Product Term Gate)

1.00

—

1.00

—

1.00

—

1.67

—

tOESi

1.00

—

1.00

—

1.40

—

2.33

—

tOESi_PT

1.00

—

1.00

—

1.00

—

1.67

—

tOESRPWi

Asynchronous Set/Reset Pulse Width

—

2.50

—

2.50

—

2.50

—

4.17

Timing v.2.2

1. Internal parameters are not tested and are for reference only. Refer to the timing model in this data sheet for details.

2. tPLL_DELAY is the unit of increment by which the clock signal can be incremented. The PLL can adjust the clock signal by up to tRANGE (as

given in the sysCLOCK PLL Timing section) in either direction in steps of size tPLL_DELAY.

ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters

1 (Continued)

Over Recommended Operating Conditions

Parameter

Description

-3

-32

-35

-5

Units

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

LX256VCF2085 Datasheet(PDF) 35 Page - Lattice Semiconductor

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