LX256VCF2085 datasheet(6/72 Pages) LATTICE

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Lattice Semiconductor

ispGDX2 Family Data Sheet

The four data inputs to the 4:1 MUX come from the GRP. The output of this MUX connects to the output register. A

fast feedback path from the MUX to the GRP allows wider MUXes to be built. Table 2 summarizes the various MUX

sizes and delay levels.

Table 2. MUX Size Versus Internal Delay

Figure 3. ispGDX2 Family MRB

Control Array

The control array generates control signals for the 16 MRBs within a GDX Block. The true and complement forms

of 32 inputs from the GRP are available in the control array. The 20 NAND terms can use any or all of these inputs

to form the control array outputs. Two AND terms are combined with a NOR term to form Set/Reset and OE sig-

nals. Figure 4 illustrates the control array.

MUX Sizes

Levels of Internal GRP Delays

4:1

One Level

Up to 16:1

Two Levels

Up to 64:1

Three Levels

Up to 188:1 (with ispGDX2-256)

Four Levels

Reg/Latch

S/R

D/L

ClK

Set

Reset

D/L

ClK

Set

Reset

2-4

to IN_Reg(n-1)

to IN_Reg(n+1)

from

Out_Reg(n-1)

from

Out_Reg(n+1)

FIFO Out*

from IN_Reg(n-1)

from IN_Reg(n+1)

to Out_Reg(n-1)

to Out_Reg(n+1)

Flags*

(FIFO, SERDES

or PLL)

*Selected MRBs see Logic Signal Connection Table for details

VCC

Delay

Global Resetb

From GRP

MUX Select

Control Array Signals

MUX

Select

Global

Signals

Global

Signals

GDX

Control Array

TOE

To GRP

D/L

ClK

Set

Reset

Out

Reg/Latch

Input

Reg/Latch

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