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LX256VCF2085 Datasheet(PDF) 45 Page - Lattice Semiconductor |
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LX256VCF2085 Datasheet(HTML) 45 Page - Lattice Semiconductor |
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45 / 72 page  Lattice Semiconductor ispGDX2 Family Data Sheet 45 sysCLOCK PLL Timing Over Recommended Operating Conditions Symbol Parameter Conditions Min Max Units tPWH Input clock, high time 80% to 80% 0.5 — ns tPWL Input clock, low time 20% to 20% 0.5 — ns tR, tF Input Clock, rise and fall time 20% to 80% — 3.0 ns tINSTB Input clock stability, cycle to cycle (peak) — +/- 300 ps fMDIVIN M Divider input, frequency range 10 320 MHz fMDIVOUT M Divider output, frequency range 10 320 MHz fNDIVIN N Divider input, frequency range 10 320 MHz fNDIVOUT N Divider output, frequency range 10 320 MHz fVDIVIN V Divider input, frequency range 100 400 MHz fVDIVOUT V Divider output, frequency range 10 320 MHz tOUTDUTY Output clock, duty cycle 40 60 % tJIT(CC) Output clock, cycle to cycle jitter (peak) Clean reference 1: 10 MHz ≤ fMDIVOUT ≤ 40 MHz or 100 MHz ≤ fVDIVIN ≤ 160 MHz — +/- 600 ps Clean reference 1: 40 MHz ≤ fMDIVOUT ≤ 320 MHz and 160 MHz ≤ fVDIVIN ≤ 400 MHz — +/- 150 ps TJIT(PERIOD) 2 Output clock, period jitter (peak) Clean reference 1: 10 MHz ≤ fMDIVOUT ≤ 40 MHz or 100 MHz ≤ fVDIVIN ≤ 160 MHz — +/- 600 ps Clean reference 1: 40 MHz ≤ fMDIVOUT ≤ 320 MHz and 160 MHz ≤ fVDIVIN ≤ 400 MHz — +/- 150 ps tCLK_OUT_DLY Input clock to CLK_OUT delay Internal feedback — 3.4 ns tPHASE Input clock to external feedback delta External feedback — 500 ps tLOCK Time to acquire phase lock after input stable — 25 us tPLL_DELAY Delay increment (Lead/Lag) Typical = +/- 250ps +/- 120 +/- 550 ps tRANGE Total output delay range (lead/lag) +/- 0.84 +/- 3.85 ns tPLL_RSTW Minimum reset pulse width 1.8 — ns 1. This condition assures that the output phase jitter will remain within specification. Jitter specification is based on optimized M, N and V set- tings determined by the ispLEVER software. 2. Accumulated jitter measured over 10,000 waveform samples |
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