LX256VCF2085 datasheet(41/72 Pages) LATTICE

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Lattice Semiconductor

ispGDX2 Family Data Sheet

Deserializer Timing

Lock-in Timing

Symbol

Description

Mode

Conditions

Min.

Max.

Units

fDSIN

SIN Frequency Deviation from REFCLK

8B10B/

10B12B

-100

100

ppm

eoSIN

SIN Eye Opening Tolerance

All

Notes 1, 2

0.45

UIPP

ber

Bit Error Rate

All

-12

Bits

tHSIOUTVALIDPRE

RXD, SYDT Valid Time Before RECCLK Fall-

ing Edge

All

Note 3

tRCP/2 - 0.7

tHSIOUTVALIDPOST

RXD, SYDT Valid Time

After RECCLK Falling Edge

All

Note 3

tRCP/2 - 0.7

tDSIN

Bit 0 of SIN Delay to RXD Valid at RECCLK

Falling edge

All

1.5 tRCP +

4.5Bt + 2

1.5 tRCP +

4.5Bt + 10

1. Eye opening based on jitter frequency of 100KHz.

2. Lower frequency operation assumes maximum eye closure of 800ps.

3. Internal timing for reference only.

TRAINING SEQUENCE

SS MODE DATA TRANSFER

SIN

CAL

SYDT

RXD(0:7)

CDRX_SS LOCK-IN (DE-SKEW) TIMING

DATA (SERIAL)

MIN. 1200 SYNCPAT

MIN. 1100 LS CYCLE

SYNCPAT

DATA (PARALLEL)

SUSYNC

HDSYNC

SIN

SYDT

RXD(0:9)

CDR_10B12B LOCK-IN TIMING

DATA (SERIAL)

1024 SYNCPAT

SYNCPAT

DATA (PARALLEL)

LX256VCF2085 Datasheet(PDF) 41 Page - Lattice Semiconductor

LX256VCF2085 Datasheet(HTML) 41 Page - Lattice Semiconductor

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