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LX256VCF2085 Datasheet(PDF) 27 Page - Lattice Semiconductor |
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LX256VCF2085 Datasheet(HTML) 27 Page - Lattice Semiconductor |
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27 / 72 page  Lattice Semiconductor ispGDX2 Family Data Sheet 27 ispGDX2V/B/C, ispGDX2EV/EB/EC External Switching Characteristics Over Recommended Operating Conditions Parameter Description -3 -32 -35 -5 Units Min. Max. Min. Max. Min. Max. Min. Max. Output Paths tPD Data From Input Pin to Output Pin — 3.0 — 3.2 — 3.5 — 5.0 ns tPD_SEL Data From Global Select Pin to Output Pin — 2.8 — 3.0 — 3.3 — 4.7 ns tCO Global Clock to Output — 2.9 — 3.1 — 3.2 — 5.4 ns tOPS Set-up Time Before Global Clock 2.0 — 2.0 — 2.0 — 3.0 — ns tOPH Hold Time After Global Clock 0.0 — 0.0 — 0.0 — 0.0 — ns tOPCES PT Clock Enable Setup Time Before Global Clock 3.0 — 3.0 — 4.1 — 6.9 — ns tOPCEH PT Clock Enable Hold Time After Global Clock 0.0 — 0.0 — 0.0 — 0.0 — ns tOPRSTO External Reset Pin to Output Delay — 5.3 — 6.0 — 6.0 — 10.0 ns Input Paths tIPS Set-up Time Before Global Clock 0.5 — 0.5 — 0.5 — 0.9 — ns tIPSZ Set-up Time Before Global Clock (Zero Hold Time) 2.0 — 2.0 — 2.0 — 3.0 — ns tIPH Hold Time After Global Clock 1.0 — 1.0 — 1.0 — 1.7 — ns tIPHZ Hold Time After Global Clock (Zero Hold Time) 0.0 — 0.0 — 0.0 — 0.0 — ns tIPCES PT Clock Enable Setup Time Before Global Clock 3.1 — 3.1 — 3.1 — 5.1 — ns tIPCEH PT Clock Enable Hold Time After Global Clock 0.0 — 0.0 — 0.0 — 0.0 — ns tIPRSTO External Reset Pin to Output Delay — 5.6 — 6.5 — 7.5 — 12.5 ns Output Enable Paths tOECO Global Clock to Output Enabled Pin — 4.2 — 4.5 — 5.5 — 9.1 ns tOES Output Enable Register Set-up Time Before Global Clock 1.6 — 1.6 — 2.0 — 3.4 — ns tOEH Hold Time After Global Clock 0.0 — 0.0 — 0.0 — 0.0 — ns tOECES PT Clock Enable Setup Time Before Global Clock 3.5 — 3.5 — 4.1 — 6.9 — ns tOECEH PT Clock Enable Hold Time After Global Clock 0.0 — 0.0 — 0.0 — 0.0 — ns tGOE/DIS Global OE Input to Output Enable/Disable — 3.5 — 3.8 — 4.5 — 7.5 ns tTOE/DIS Test OE Input to Output Enable/Disable — 5.2 — 5.5 — 6.2 — 10.3 ns tEN/DIS Input to Output Enable/Disable — 5.2 — 5.5 — 6.2 — 10.3 ns Clock and Reset Paths tRW Width of Reset Pulse 2.5 — 2.5 — 2.5 — 4.1 — ns tCW Clock Width 1.3 — 1.5 — 1.6 — 2.7 — ns tGW Clock Width 1.5 — 1.6 — 1.6 — 2.7 — ns fMAX (Ext) Clock Frequency with External Feedback 1/(tOPS + tCO) — 204 — 196 — 192 — 119 MHz fMAX (Tog, No PLL) Clock Frequency Maximum Toggle (No PLL) — 360 — 330 — 300 — 180 MHz |
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