LX256VCF2085 datasheet(4/72 Pages) LATTICE

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Lattice Semiconductor

ispGDX2 Family Data Sheet

MUX and Register Block (MRB)

Every MRB Block has a 4:1 MUX (I/O MUX) and a set of three registers which are connected to the I/O buffers,

FIFO and sysHSI Blocks. Multiple MRBs can be combined to form large multiplexers as described below. Figure 3

shows the structure of the MRB.

Each of the three registers in the MRB can be conﬁgured as edge-triggered D-type ﬂip-ﬂop or as a level sensitive

latch. One register operates on the input data, the other output data and the last register synchronizes the output

enable function. The input and output data signals can bypass each of their registers. The polarity of the data out

and output enable signals can be selected.

The Output and OE register share the same clock and clock enable signals. The Input register has a separate clock

and clock enable. The initialization signals of each register can be independently conﬁgured as Set or Reset. These

registers have programmable polarity control for Clock, Clock Enable and Set/Reset. The output enable register

input can be set either by one of the two output enables generated locally from the Control Array or from one of the

four (two in 64 I/O) Global OE enable pins. In addition to the local clock and clock enable signals, each MRB has

access to Global Clock, Clock Enable, Reset and TOE nets.

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