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LX256VCF2085 Datasheet(PDF) 19 Page - Lattice Semiconductor |
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LX256VCF2085 Datasheet(HTML) 19 Page - Lattice Semiconductor |
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19 / 72 page  Lattice Semiconductor ispGDX2 Family Data Sheet 19 Figure 15. Operation in SERDES Only Mode 1, 2 SERDES FIFO GDX Block GRP 10 Serial Data In (SIN) Serial Data Out (SOUT) RXD Parallel Data TXD Parallel Data DIN DOUT RCLK RE FIFORSTb SYDT CDRRSTb FULL EMPTY Output Reg/ Latch Output Reg/ Latch Output Reg/ Latch 10 Input Reg/ Latch Delay POR RESETb Pre-Assigned Pins WE PT-CLK/CE(0:3) RECCLK WCLK GCLK/CE(0:3) Input Reg/ Latch Input Reg/ Latch CAL Notes: 1. Some pins shared. See Logic Signal Connections table for details. 2. For SERDES only mode programmable bit holds FIFO in reset. Input registers used for DOUT, and RECCLK configured as latches and held in pass through. |
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