LX256VCF2085 datasheet(30/72 Pages) LATTICE

30 / 72 page

Lattice Semiconductor

ispGDX2 Family Data Sheet

Figure 19. ispGDX2 Timing Model Diagram (with sysHSI and FIFO Receive Mode)

Figure 20. ispGDX2 Timing Model Diagram (with sysHSI Transmit Mode)

FIFO

HSIFIFORST

Read

Clock

Read

Enable

Write CLK

FIFOWCLK

FIFOREN

FIFORCLK

sysHSI

(RXD)

Recovered

Clock

FULL, EMPTY

to I/O Cell

(Output Path Flags)

from I/O Cell

(RCLK)

from I/O Cell

(RE)

RESET

HSI Controls

HSI Flags

CSLOCK

to I/O Cell

(Output Path Flag)

SYDT

to I/O Cell

(SYDT and Output

Path Flags)

Serial Data

HSISIN

from I/O Cell

(SIN)

Data In

FIFODATAIN

Data Out

(RXD)

from I/O Cell

(Control)

CAL

HSICTRLCAL

to I/O Cell

(RECCLK)

Data Out

to I/O Cell

(DOUT)

FIFO Flags

from I/O Cell

(Global RESET)

from I/O Cell

(I/O RESET)

Reference Clock

HSIREFCLK

from I/O Cell

(REFCLK)

Source

Synchronous Clock

HSISSCLKIN

from I/O Cell

(SSCLKIN)

sysHSI

(TXD)

Serial

Data Out

to I/O Cell

(SOUT)

Data In

HSITXDATA

from I/O Cell

(TXD)

Reference Clock

HSIREFCLK

from I/O Cell

(REFCLK)

Source

Synchronous Clock

to I/O Cell

(SSCLKOUT)

LX256VCF2085 Datasheet(PDF) 30 Page - Lattice Semiconductor

LX256VCF2085 Datasheet(HTML) 30 Page - Lattice Semiconductor

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