LX256VCF2085 datasheet(67/72 Pages) LATTICE

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Lattice Semiconductor

ispGDX2 Family Data Sheet

TOE

AB10

1. The signals in this column route to/from the assigned pins of the associated I/O cell.

2. The signals in this column use the I/O cell. If a receiver signal is present in the I/O cell, the associated pin is available for output only. When

transmit data (TXD) is present in the cell, the associated pin is available for input only.

3. The DOUT outputs are routed to GRP through the input register of the cell and the DIN inputs are routed direct from the associated pins in

FIFO only mode. In SERDES with FIFO mode, the FULL and EMPTY ﬂags are routed to the associated pins through the output MUX and

the pins.

4. If the Source Synchronous Receiver is used in the HSI Block, this pin is unavailable for another use and must be left unconnected.

5. The SYDT signal has two routing options. If direct output through the dedicated pin is used, the I/O cell (the whole HSI Block) is not avail-

able for transmitter. The SYDT in the I/O Cell column is routed to the GRP through the input register of the cell and frees the I/O cell for

transmitter.

6. FIFO_STRDb ﬂag output is used in SERDES with FIFO Mode only.

7. sysHSI Source Synchronous Receive Mode is not available for channel 3A.

ispGDX2-256 Logic Signal Connections (Continued)

Signal

Name

sysIO

Bank

LVDS

Pair/Polarity

GDX

Block MRB

SERDES Mode

I/O Pin

SERDES Mode

I/O Cell

FIFO Mode I/O

Cell/Pin

484

fpBGA

LX256VCF2085 Datasheet(PDF) 67 Page - Lattice Semiconductor

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