LX256VCF2085 datasheet(51/72 Pages) LATTICE

51 / 72 page

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2-64 Power Supply and NC Connections

HSImA_TXDw, HSImB_ TXD

Internal Signal – Parallel data in bit w for sysHSI BLOCK m channel A, B.

HSImA_RXDw, HSImB_ RXD

Internal Signal – Parallel data out bit w for sysHSI BLOCK m channel A, B.

Source Synchronous Functions

SS_SCLKIN0P, SS_SCLKIN1P

Input – Positive sense clock input for Source Synchronous group A, B.

SS_SCLKIN0N, SS_SCLKIN1N

Input – Negative (minus) sense clock input for Source Synchronous group A, B.

SS_CLKOUT0N, SS_CLKOUT1P

Output – Positive sense clock output for Source Synchronous group A, B.

SS_CLKOUT0N, SS_CLKOUT1N

Output – Negative (minus) sense clock output for Source Synchronous group A, B.

CAL

Input – Initiates source synchronous calibration sequence.

1. m, w, x, y and z are variables.

2. Not on ispGDX2-64

Signal

ispGDX2-64 (100-Ball fpBGA)

VCC

A1, K10

VCCO0

VCCO1

F10

VCCO2

E10

VCCO3

VCCO4

VCCO5

VCCO6

VCCO7

VCCJ

VCCP0

GNDP0

GND

A10, B9, C8, E6, E5, F6, F5, H3, J2

1. All grounds must be electrically connected at the board level.

2. Pin orientation A1 starts from the upper left corner of the top

side view with alphabetical order ascending vertically and

numerical order ascending horizontally.

Signal Descriptions

1 (Continued)

Signal Names

Description

LX256VCF2085 Datasheet(PDF) 51 Page - Lattice Semiconductor

LX256VCF2085 Datasheet(HTML) 51 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL