HD6433644R datasheet(340/549 Pages) RENESAS

340 / 549 page

Section 10 Serial Communication Interface

Rev. 6.00 Sep 12, 2006 page 320 of 526

REJ09B0326-0600

Start receive

error processing

End of receive

error processing

Clear bits OER, PER,

FER to 0 in SSR

Yes

OER = 1?

Yes

FER = 1?

Break?

Yes

PER = 1?

Overrun error

processing

Framing error

processing

(A)

Parity error

processing

If a receive error has

occurred, read bits OER,

PER, and FER in SSR to

identify the error, and after

carrying out the necessary

error processing, ensure

that bits OER, PER, and

FER are all cleared to 0.

Reception cannot be

resumed if any of these

bits is set to 1. In the case

of a framing error, a break

can be detected by reading

the value of the RXD pin.

Figure 10.13 Example of Data Reception Flowchart (Asynchronous Mode) (cont)

SCI3 operates as follows when receiving data.

SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal

synchronization and begins reception. Reception is carried out in accordance with the relevant data

transfer format in table 10.14. The received data is first placed in RSR in LSB-to-MSB order, and

then the parity bit and stop bit(s) are received. SCI3 then carries out the following checks.

• Parity check

SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even)

set in bit PM in the serial mode register (SMR).

• Stop bit check

SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked.

• Status check

SCI3 checks that bit RDRF is set to 1, indicating that the receive data can be transferred from

RSR to RDR.

HD6433644R Datasheet(PDF) 340 Page - Renesas Technology Corp

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