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HD6433644R Datasheet(PDF) 142 Page - Renesas Technology Corp

Part # HD6433644R
Description  8-Bit Single-Chip Microcomputer
PDF  549 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6433644R Datasheet(HTML) 142 Page - Renesas Technology Corp

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Section 6 ROM
Rev. 6.00 Sep 12, 2006 page 122 of 526
REJ09B0326-0600
Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8/3644F, H8/3643F, or
H8/3642AF measures the low period of the asynchronous SCI communication data transmitted
continuously from the host (figure 6.10). The data format should be set as 8-bit data, 1 stop bit, no
parity. The chip calculates the bit rate of the transmission from the host from the measured low
period (9 bits), and transmits one H'00 byte to the host to indicate the end of bit rate adjustment.
The host should confirm that this adjustment end indication has been received normally, and
transmit one H'55 byte to the chip. If reception cannot be performed normally, initiate boot mode
again (reset), and repeat the above operations. Depending on the host’s transmission bit rate and
the chip’s system clock oscillation frequency (fOSC), there will be a discrepancy between the bit
rates of the host and the chip. To insure correct SCI operation, the host’s transfer bit rate should be
set to 2400, 4800, or 9600 bps*1. Table 6.10 shows typical host transfer bit rates and system clock
oscillation frequency for which automatic adjustment of the chip’s bit rate is possible. Boot mode
should be used within this system clock oscillation frequency range*2.
Notes: 1. Only use a host bit rate setting of 2400, 4800, or 9600 bps. No other bit rate setting
should be used.
2. Although the chip may also perform automatic bit rate adjustment with bit rate and
system clock oscillation frequency combinations other than those shown in table 6.10,
a degree of error will arise between the bit rates of the host and the chip, and
subsequent transfer will not be performed normally. Therefore, only a combination of
bit rate and system clock oscillation frequency within one of the ranges shown in table
6.10 can be used for boot mode execution.
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop
bit
Low period (9 bits) measured (H'00 data)
High period
(1 or more
bits)
Figure 6.10 Measurement of Low Period in Transmit Data from Host



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