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HD6433644R Datasheet(PDF) 138 Page - Renesas Technology Corp

Part # HD6433644R
Description  8-Bit Single-Chip Microcomputer
PDF  549 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6433644R Datasheet(HTML) 138 Page - Renesas Technology Corp

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Section 6 ROM
Rev. 6.00 Sep 12, 2006 page 118 of 526
REJ09B0326-0600
6.5.3
Erase Block Register 2 (EBR2)
EBR2 is an 8-bit register that specifies small flash-memory blocks for programming or erasure.
EBR2 is initialized to H'00 upon reset, in sleep mode, subsleep mode, watch mode, and standby
mode, and when 12 V is not applied to FVPP. When a bit in EBR2 is set to 1, the corresponding
block is selected and can be programmed and erased. The erase block map is shown in figure 6.7,
and the correspondence between bits and erase blocks is shown in table 6.8.
Bit
7
6
5
4
3
2
1
0
SB7
SB6
SB5
SB4
SB3
SB2
SB1
SB0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Note:
* Word access cannot be used on this register; byte access must be used. For
information on access to this register, see note 11 in section 6.9, Flash Memory
Programming and Erasing Precautions. LB3 is invalid in the H8/3643F, and LB3 and
LB2 are invalid in the H8/3642AF.
Bits 7 to 0
Small Block 7 to 0 (SB7 to SB0): These bits select small blocks (SB7 to SB0) to be
programmed and erased.
Bits 7 to 0:
SB7 to SB0
Description
0
Block SB7 to SB0 is not selected
(initial value)
1
Block SB7 to SB0 is selected



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