HD6433644R datasheet(137/549 Pages) RENESAS

137 / 549 page

Section 6 ROM

Rev. 6.00 Sep 12, 2006 page 117 of 526

REJ09B0326-0600

6.5.2

Erase Block Register 1 (EBR1)

EBR1 is an 8-bit register that specifies large flash-memory blocks for programming or erasure.

EBR1 is initialized to H'F0 upon reset, in sleep mode, subsleep mode, watch mode, and standby

mode, and when 12 V is not applied to FVPP. When a bit in EBR1 is set to 1, the corresponding

block is selected and can be programmed and erased. The erase block map is shown in figure 6.7,

and the correspondence between bits and erase blocks is shown in table 6.8.

Bit



LB3

LB2

LB1

LB0

Initial value

Read/Write



R/W*

Note:

* Word access cannot be used on this register; byte access must be used. For

information on access to this register, see note 11 in section 6.9, Flash Memory

Programming and Erasing Precautions. LB3 is invalid in the H8/3643F, and LB3 and

LB2 are invalid in the H8/3642AF.

Bits 7 to 4



Reserved: Bits 7 to 4 are reserved; they are always read as 1, and cannot be

modified.

Bits 3 to 0



Large Block 3 to 0 (LB3 to LB0): These bits select large blocks (LB3 to LB0) to be

programmed and erased.

Bits 3 to 0:

LB3 to LB0

Description

Block LB3 to LB0 is not selected

(initial value)

Block LB3 to LB0 is selected

HD6433644R Datasheet(PDF) 137 Page - Renesas Technology Corp