HD6433644R datasheet(134/549 Pages) RENESAS

134 / 549 page

Section 6 ROM

Rev. 6.00 Sep 12, 2006 page 114 of 526

REJ09B0326-0600

6.4.5

Pin Configuration

The flash memory is controlled by means of the pins shown in table 6.6.

Table 6.6

Flash Memory Pins

Pin Name

Abbreviation

Input/Output

Function

Programming power

FVPP

Power supply

Apply 12.0 V

Mode pin

TEST

Input

Sets H8/3644F operating mode

Transmit data

TXD

Output

SCI3 transmit data output

Receive data

RXD

Input

SCI3 receive data input

The transmit data pin and receive data pin are used in boot mode.

6.4.6

The registers used to control the on-chip flash memory are shown in table 6.7.

Table 6.7

Flash Memory Registers

Abbreviation

R/W

Initial Value

Address

Flash memory control register

FLMCR

R/W

H'00

H'FF80

Erase block register 1

EBR1

R/W

H'F0

H'FF82

Erase block register 2

EBR2

R/W

H'00

H'FF83

The FLMCR, EBR1, and EBR2 registers are valid only when programming and erasing flash

memory, and can only be accessed when 12 V is applied to the FVPP pin. When 12 V is not

applied to the FVPP pin, addresses H'FF80 to H'FF83 cannot be modified and are always read as

H'FF.

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