HD6433644R datasheet(131/549 Pages) RENESAS

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Section 6 ROM

Rev. 6.00 Sep 12, 2006 page 111 of 526

REJ09B0326-0600

6.4

Flash Memory Overview

6.4.1

Principle of Flash Memory Operation

Table 6.5 illustrates the principle of operation of the on-chip flash memory in the H8/3644F,

H8/3643F, and H8/3642AF.

Like EPROM, flash memory is programmed by applying a high gate-to-drain voltage that draws

hot electrons generated in the vicinity of the drain into a floating gate. The threshold voltage of a

programmed memory cell is therefore higher than that of an erased cell. Cells are erased by

grounding the gate and applying a high voltage to the source, causing the electrons stored in the

floating gate to tunnel out. After erasure, the threshold voltage drops. A memory cell is read like

an EPROM cell, by driving the gate to a high level and detecting the drain current, which depends

on the threshold voltage. Erasing must be done carefully, because if a memory cell is overerased,

its threshold voltage may become negative, causing the cell to operate incorrectly.

Section 6.7.6, Erase Flowcharts and Sample Programs, shows optimal erase control flowcharts and

sample programs.

Table 6.5

Principle of Memory Cell Operation

Program

Erase

Read

Memory

cell

Vg = VPP

Vs = VPP

Open

Vg = VCC

Memory

array

VPP

0 V

Open

VPP

Open

0 V

VCC

0 V

HD6433644R Datasheet(PDF) 131 Page - Renesas Technology Corp