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HD6433644R Datasheet(PDF) 133 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 133 Page - Renesas Technology Corp |
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133 / 549 page ![]() Section 6 ROM Rev. 6.00 Sep 12, 2006 page 113 of 526 REJ09B0326-0600 6.4.4 Block Diagram Figure 6.6 shows a block diagram of the flash memory. Internal data bus (lower) Bus interface/control section FLMCR EBR1 EBR2 8 Internal data bus (upper) 8 TEST Operating mode Upper byte (even address) On-chip flash memory (32 kbytes) H'0000 H'0002 H'0004 H'0001 H'0003 H'0005 H'7FFC H'7FFE H'7FFD H'7FFF Lower byte (odd address) Legend: FLMCR: Flash memory control register EBR1: Erase block register 1 EBR2: Erase block register 2 Figure 6.6 Block Diagram of Flash Memory (Example of the H8/3644F) |
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