HD6433644R datasheet(136/549 Pages) RENESAS

136 / 549 page

Section 6 ROM

Rev. 6.00 Sep 12, 2006 page 116 of 526

REJ09B0326-0600

Bit 2



Program-Verify Mode (PV)*: Bit 2 selects transition to or exit from program-verify

mode.

Bit 2: PV

Description

Exit from program-verify mode

(initial value)

Transition to program-verify mode

Note:

* Do not set multiple bits simultaneously.

Do not release or cut the VCC or VPP power supply while a bit is set.

Bit 1



Erase Mode (E)*1*2: Bit 1 selects transition to or exit from erase mode.

Bit 1: E

Description

Exit from erase mode

(initial value)

Transition to erase mode

Notes: 1. Do not set multiple bits simultaneously.

Do not release or cut the VCC or VPP power supply while a bit is set.

2. P bit and E bit setting should be carried out in accordance with the program/erase

algorithms shown in section 6.7, Programming and Erasing Flash Memory.

A watchdog timer setting should be made beforehand to prevent the P or E bit from

being set for longer than the specified time.

See section 6.9, Flash Memory Programming and Erasing Precautions, for more

information on the use of these bits.

Bit 0



Program Mode (P)*1*2: Bit 0 selects transition to or exit from program mode.

Bit 0: P

Description

Exit from program mode

(initial value)

Transition to program mode

Notes: 1. Do not set multiple bits simultaneously.

Do not release or cut the VCC or VPP power supply while a bit is set.

2. P bit and E bit setting should be carried out in accordance with the program/erase

algorithms shown in section 6.7, Programming and Erasing Flash Memory.

A watchdog timer setting should be made beforehand to prevent the P or E bit from

being set for longer than the specified time.

See section 6.9, Flash Memory Programming and Erasing Precautions, for more

information on the use of these bits.

HD6433644R Datasheet(PDF) 136 Page - Renesas Technology Corp

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