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HD6433644R Datasheet(PDF) 182 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 182 Page - Renesas Technology Corp |
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182 / 549 page ![]() Section 6 ROM Rev. 6.00 Sep 12, 2006 page 162 of 526 REJ09B0326-0600 tOSC1 3.0 to 5.5 V 12 ±0.6 V 12 ±0.6 V VCC + 2 V to 11.4 V VCCV VCCV φ VCC VPP (boot mode) Period during which flash memory access is prohibited and VPP flag set/clear period VPP (user program mode) RES 0 µs min. 0 µs min. Timing of boot program branch to RAM space Min. 10 φ cycles (When RES is low) 0 µs min. 0 to VCCV 0 to VCCV Figure 6.23 VPP Power-On and Cut-Off Timing 6. Do not apply 12 V to the FVPP pin during normal operation. To prevent erroneous programming or erasing due to program runaway, etc., apply 12 V to the FVPP pin only when programming or erasing flash memory. If overprogramming or overerasing occurs due to program runaway, etc., the memory cells may not operate normally. A system configuration in which a high level is constantly applied to the FVPP pin should be avoided. Also, while a high level is applied to the FVPP pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. |
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