HD6433644R datasheet(183/549 Pages) RENESAS

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Section 6 ROM

Rev. 6.00 Sep 12, 2006 page 163 of 526

REJ09B0326-0600

7. Design a current margin into the programming voltage (VPP) power supply.

Insure that VPP remains within the range 12.0 V ±0.6 V (11.4 V to 12.6 V) during

programming and erasing. Programming and erasing may become impossible outside this

range.

8. Insure that peak overshoot at the FVPP and TEST pins does not exceed the maximum rating.

Connect bypass capacitors as close as possible to the FVPP and TEST pins.

In boot mode start-up, also, bypass capacitors should be connected to the TEST pin in the same

way.

0.01

µF

FVPP

H8/3644F

1.0

µF

12 V

Figure 6.24 Example of VPP Power Supply Circuit Design

9. Use the recommended algorithms when programming and erasing flash memory.

The recommended algorithms enable programming and erasing to be carried out without

subjecting the device to voltage stress or sacrificing program data reliability. When setting the

program (P) or erase (E) bit in the flash memory control register (FLMCR), the watchdog

timer should be set beforehand to prevent the specified time from being exceeded.

10. For comments on interrupt handling while flash memory is being programmed or erased, see

section 6.7.9, Interrupt Handling during Flash Memory Programming/Erasing.

11. Notes on accessing flash memory control registers

a. Flash memory control register access state in each operating mode

The H8/3644F, H8/3643F, and H8/3642AF have flash memory control registers located at

addresses H'FF80 (FLMCR), H'FF82 (EBR1), and H'FF83 (EBR2). These registers can

only be accessed when 12 V is applied to the flash memory programming power supply

pin, FVPP.

b. To check for 12 V application/non-application in user mode

When address H'FF80 is accessed in user mode, if 12 V is being applied to FVPP, FLMCR

is read/written to, and its initial value after reset is H'80. When 12 V is not being applied to

FVPP, FLMCR is a reserved area that cannot be modified and always reads H'FF. Since bit

7 (corresponding to the VPP bit) is set to 1 at this time regardless of whether or not 12 V is

applied to FVPP, application or release of 12 V to FVPP cannot be determined simply from

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