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HD6433644R Datasheet(PDF) 303 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 303 Page - Renesas Technology Corp |
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303 / 549 page  Section 10 Serial Communication Interface Rev. 6.00 Sep 12, 2006 page 283 of 526 REJ09B0326-0600 Bit 0 Start Flag (STF): Bit 0 controls the start of a transfer. Setting this bit to 1 causes SCI1 to start transferring data. During the transfer or while waiting for the first clock pulse, this bit remains set to 1. It is cleared to 0 upon completion of the transfer. It can therefore be used as a busy flag. Bit 0: STF Description 0 Read: Indicates that transfer is stopped (initial value) Write: Invalid 1 Read: Indicates transfer in progress Write: Starts a transfer operation Serial Data Register U (SDRU) Bit 7 6 5 4 3 2 1 0 SDRU7 SDRU6 SDRU5 SDRU4 SDRU3 SDRU2 SDRU1 SDRU0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W R/W R/W R/W R/W SDRU is an 8-bit read/write register. It is used as the data register for the upper 8 bits in 16-bit transfer (SDRL is used for the lower 8 bits). Data written to SDRU is output to SDRL starting from the least significant bit (LSB). This data is then replaced by LSB-first data input at pin SI1, which is shifted in the direction from the most significant bit (MSB) toward the LSB. SDRU must be written or read only after data transmission or reception is complete. If this register is written or read while a data transfer is in progress, the data contents are not guaranteed. The SDRU value upon reset is undefined. Serial Data Register L (SDRL) Bit 7 6 5 4 3 2 1 0 SDRL7 SDRL6 SDRL5 SDRL4 SDRL3 SDRL2 SDRL1 SDRL0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W R/W R/W R/W R/W |
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