HD6433644R datasheet(304/549 Pages) RENESAS

304 / 549 page

Section 10 Serial Communication Interface

Rev. 6.00 Sep 12, 2006 page 284 of 526

REJ09B0326-0600

SDRL is an 8-bit read/write register. It is used as the data register in 8-bit transfer, and as the data

In 8-bit transfer, data written to SDRL is output from pin SO1 starting from the least significant bit

(LSB). This data is then replaced by LSB-first data input at pin SI1, which is shifted in the

direction from the most significant bit (MSB) toward the LSB.

In 16-bit transfer, operation is the same as for 8-bit transfer, except that input data is fed in via

SDRU.

SDRL must be written or read only after data transmission or reception is complete. If this register

is read or written while a data transfer is in progress, the data contents are not guaranteed.

The SDRL value upon reset is undefined.

10.2.3

Operation in Synchronous Mode

Data can be sent and received in an 8-bit or 16-bit format, with an internal or external clock

selected as the clock source. Overrun errors can be detected when an external clock is used.

Clock: The serial clock can be selected from a choice of eight internal clocks and an external

clock. When an internal clock source is selected, pin SCK1 becomes the clock output pin. When

continuous clock output mode is selected (SCR1 bits SNC1 and SNC0 are set to 10), the clock

signal (

φ/1024 to φ/2) selected in bits CKS2 to CKS0 is output continuously from pin SCK1. When

an external clock is used, pin SCK1 is the clock input pin.

Data Transfer Format: Figure 10.2 shows the data transfer format. Data is sent and received

starting from the least significant bit, in LSB-first format. Transmit data is output from one falling

edge of the serial clock until the next rising edge. Receive data is latched at the rising edge of the

serial clock.

SCK

SO /SI

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Figure 10.2 Transfer Format

HD6433644R Datasheet(PDF) 304 Page - Renesas Technology Corp