SH7021 datasheet(345/509 Pages) RENESAS

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Table 12.1

Pin Configuration

Abbreviation

I/O

Function

Watchdog timer overflow

WDTOVF

Outputs the counter overflow signal in

the watchdog mode

12.1.4

Table 12.2 summarizes the three WDT registers. They are used to select the clock, switch the

WDT mode, and control the reset signal.

Table 12.2

WDT Registers

Address

Name

Abbreviation

R/W

Initial Value

Write*1

Read*2

Timer

control/status

TCSR

R/(W)*3

H'18

H'5FFFFB8

Timer counter

TCNT

R/W

H'00

H'5FFFFB9

Reset

control/status

RSTCSR

R/(W)*3

H'3F

H'5FFFFBA

H'5FFFFBB

Notes: 1. Write by word transfer. It cannot be written in byte or long word.

2. Read by byte transfer. It cannot be read in word or long word.

3. Only 0 can be written in bit 7 to clear the flag.

12.2

12.2.1

Timer Counter (TCNT)

The TCNT is an eight-bit readable and writable upcounter. The TCNT differs from other registers

in that it is more difficult to write. See section 12.2.4, Register Access, for details. When the timer

enable bit (TME) in the timer control/status register (TCSR) is set to 1, the timer counter starts

counting pulses of an internal clock source selected by clock select bits 2–0 (CKS2–CKS0) in the

TCSR. When the value of the TCNT overflows (changes from H'FF–H'00), a watchdog timer

overflow signal (

WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode

selected in the WT/

IT bit of the TCSR. The TCNT is initialized to H'00 by a reset and when the

TME bit is cleared to 0. It is not initialized in the standby mode.

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