SH7021 datasheet(347/509 Pages) RENESAS

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RENESAS 331

Bit 5: TME

Description

Timer disabled: TCNT is initialized to H'00 and count-up stops (initial

value)

Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt

is generated when TCNT overflows.

•

Bits 4 and 3 (reserved): These bits always read as 1. The write value should always be 1.

•

Bits 2–0 (clock Select 2–0 (CKS2–CKS0)): CKS2–CKS0 select one of eight internal clock

sources for input to the TCNT. The clock signals are obtained by dividing the frequency of the

system clock (

φ).

Description

Bit 2:

CKS2

Bit 1:

CKS1

Bit 0:

CKS0

Clock Source

Overflow Interval* (

φ = 20 MHz)

φ/2 (initial value)

25.6

µs

φ/64

819.2

µs

φ/128

1.6 ms

φ/256

3.3 ms

φ/512

6.6 ms

φ/1024

13.1 ms

φ/4096

52.4 ms

φ/8192

104.9 ms

Note:

The overflow interval listed is the time from when the TCNT begins counting at H'00 until an

overflow occurs.

12.2.3

Reset Control/Status Register (RSTCSR)

The RSTCSR is an eight-bit readable and writable register that controls output of the reset signal

generated by timer counter (TCNT) overflow and selects the internal reset signal type. The

RSTCSR differs from other registers in that it is more difficult to write. See section 12.2.4

RES

pin, but is not initialized by the internal reset signal generated by the overflow of the WDT. It is

initialized to H'1F in standby mode.

Bit:

Bit name:

WOVF

RSTE

RSTS

—

Initial value:

R/W:

R/(W)*

R/W

—

Note:

Only 0 can be written in bit 7 to clear the flag.

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