SH7021 datasheet(346/509 Pages) RENESAS

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RENESAS 330

Bit:

Bit name:

Initial value:

R/W:

R/W

12.2.2

Timer Control/Status Register (TCSR)

The timer control/status register (TCSR) is an eight-bit readable and writable register. The TCSR

differs from other registers in being more difficult to write. See section 12.2.4, Register Access,

for details. Its functions include selecting the timer mode and clock source. Bits 7–5 are initialized

to 000 by a reset or in standby mode. Bits 2–0 are initialized to 000 by a reset, but retain their

values in the standby mode.

Bit:

Bit name:

OVF

WT/IT

TME

—

CKS2

CKS1

CKS0

Initial value:

R/W:

R/(W)*

R/W

—

R/W

•

Bit 7 (overflow flag (OVF)): OVF indicates that the TCNT has overflowed from H'FF–H'00. It

is not set in the watchdog timer mode.

Bit 7: OVF

Description

No overflow of TCNT in interval timer mode (initial value)

Cleared by reading OVF, then writing 0 in OVF

TCNT overflow in the interval timer mode

•

Bit 6 (timer mode select (WT/

IT)): WT/IT selects whether to use the WDT as a watchdog

timer or interval timer. When the TCNT overflows, the WDT either generates an interval timer

interrupt (ITI) or generates a

WDTOVF signal, depending on the mode selected.

Bit 6: WT/IT

Description

Interval timer mode: interval timer interrupt to the CPU when TCNT

overflows (initial value)

Watchdog timer mode: WDTOVF signal output externally when TCNT

overflows. Section 12.2.3, Reset Control/Status Register (RSTCSR),

describes in detail what happens when TCNT overflows in the

watchdog timer mode.

•

Bit 5 (timer enable (TME)): TME enables or disables the timer.

SH7021 Datasheet(PDF) 346 Page - Renesas Technology Corp

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