R8CSLASH15 datasheet(113/277 Pages) RENESAS

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R8C/14 Group, R8C/15 Group

13. Timers

Rev.2.10

Jan 19, 2006

Page 101 of 253

REJ09B0164-0210

Figure 13.14

TZOC and PUM Registers

Timer Z Output Control Register

(3)

Symbol

Address

After Reset

TZOC

008Ah

00h

Bit Symbol

Bit Name

Function

NOTES :

3. If executing an instruction w hich changes this register w hen the TZOS bit is set to “1” (during count), the TZOS bit is

automatically set to “0” (one-shot stop) w hen the count is completed w hile the instruction is executed. If this causes

some problems, execute an instruction w hich changes this register w hen the TZOS

bit is set to “0” (one-shot stop).

b3 b2 b1 b0

TZOS

b7 b6 b5 b4

Timer Z One-shot Start Bit(1)

0 : One-shot stops

1 : One-shot starts

Reserved Bit

Set to “0”

—

(b1)

Timer Z Programmable Waveform

Generation Output Sw itch Bit(2)

0 : Outputs programmable w aveform

1 : Outputs value in P1_3 port register

TZOCNT

This bit is set to “0” w hen the output of one-shot w aveform is completed. Set the TZOS bit to “0” w hen the

w aveform output is stopped by setting the TZS bit in the TZMR register to “0” (count stop) during the one-shot

w aveform output.

This bit is enabled only w hen operating in programmable w aveform generation mode.

Nothing is assigned. When w rite, set to “0”.

When read, its content is “0”.

—

(b7-b3)

—

Timer Z Waveform Output Control Register

Symbol

Address

After Reset

PUM

0084h

00h

Bit Symbol

Bit Name

Function

INT0

_____

Pin One-shot Trigger Control

0 : INT0

_____

pin one-shot trigger disabled

Bit (Timer Z)(2)

1 : INT0

_____

pin one-shot trigger enabled

INT0

_____

Pin One-shot Trigger Polarity

Select Bit (Timer Z)(1)

NOTES :

When the INOSEG bit is enabled only w hen the INT0PL bit in the INTEN register is set to “0” (one edge).

Set the INOSTG bit to “1” w hen setting the INT0EN bit in the INTEN register and the INOSEG bit in the PUM register.

b3 b2

Function varies depending on operating

mode

b1 b0

—

(b4-b0)

b7 b6 b5 b4

Reserved Bit

Set to “0”

TZOPL

INOSEG

0 : Falling edge trigger

1 : Rising edge trigger

INOSTG

Timer Z Output Level Latch

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