R8CSLASH15 datasheet(115/277 Pages) RENESAS

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R8C/14 Group, R8C/15 Group

13. Timers

Rev.2.10

Jan 19, 2006

Page 103 of 253

REJ09B0164-0210

13.2.1

Timer Mode

Timer mode is mode to count a count source which is internally generated or Timer X underflow (see

Table 13.7 Specification of Timer Mode). The TZSC register is unused in timer mode. Figure 13.16

shows the TZMR and PUM Registers in Timer Mode.

NOTES:

1. The IR bit in the TZIC register is set to “1” (interrupt requested) when writing to the TZPR or PREZ

• TZWC bit in TZMR register is set to “0” (write to reload register and counter simultaneously)

• TZS bit in TZMR register is set to “1” (count starts)

When writing to the TZPR or PREZ register in the above state, disable an interrupt before writing.

Table 13.7

Specification of Timer Mode

Item

Specification

Count Source

f1, f2, f8, Timer X underflow

Count Operation

• Decrement

• When the timer underflows, it reloads the reload register contents before the

count continues (When Timer Z underflows, the contents of Timer Z primary

reload register is reloaded)

Divide Ratio

1/(n+1)(m+1) fi: Count source frequency

n: setting value in PREZ register, m: setting value in TZPR register

Count Start Condition Write “1” (count starts) to the TZS bit in the TZMR register

Count Stop Condition Write “0” (count stops) to the TZS bit in the TZMR register

Interrupt Request

Generation Timing

• When Timer Z underflows [Timer Z interrupt]

TZOUT Pin Function

Programmable I/O port

INT0 Pin Function

Programmable I/O port, or INT0 interrupt input

Read from Timer

The count value can be read out by reading the TZPR and PREZ registers

Write to Timer(1)

• When writing to the TZPR and PREZ registers while the count stops, the value is

written to both the reload register and counter.

• When writing to the TZPR and PREZ registers during the count while the TZWC

bit is set to “0” (writing to the reload register and counter simultaneously), the

value is written to each reload register of the TZPR and PREZ registers at the

following count source input and the data is transferred to the counter at the

second count source input and the count re-starts at the third count source input.

When the TZWC bit is set to “1” (writing to only the reload register), the value is

written to each reload register of the TZPR and PREZ registers (the data is

transferred to the counter at the following reload).

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