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R8C/15 Datasheet(PDF) 162 Page - Renesas Technology Corp |
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R8C/15 Datasheet(HTML) 162 Page - Renesas Technology Corp |
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162 / 277 page  R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU) Rev.2.10 Jan 19, 2006 Page 150 of 253 REJ09B0164-0210 Figure 15.9 Association between Transfer Clock Polarity, Phase and Transfer Data SSCK b0 SSO, SSI • When SSUMS=0 (clock synchronous communication mode), CPHS bit=0 (data change at odd edge) and CPOS bit=0 (“H” when clock stops) b1 b2 b3 b4 b5 b6 b7 SSCK CPOS=0 (“H” when clock stops) b0 SSO, SSI • When SSUMS=1 (4-wire bus communication mode) and CPHS=0 (data change at odd edge) b1 b2 b3 b4 b5 b6 b7 SSCK CPOS=1 (“L” when clock stops) SCS SSCK CPOS=0 (“H” when clock stops) SSO, SSI • When SSUMS=1 (4-wire bus communication mode), CPHS=1 (data download at odd edge) SSCK CPOS=1 (“L” when clock stops) SCS b0 b1 b2 b3 b4 b5 b6 b7 CPHS and CPOS : bits in SSMR register, SSUMS : Bits in SSMR2 register |
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