R8CSLASH15 datasheet(160/277 Pages) RENESAS

160 / 277 page

R8C/14 Group, R8C/15 Group

15. Clock Synchronous Serial I/O with Chip Select (SSU)

Rev.2.10

Jan 19, 2006

Page 148 of 253

REJ09B0164-0210

Figure 15.8

SSTDR and SSRDR Register

SS Transmit Data Register

(2)

Symbol

Address

After Reset

SSTDR

00BEh

FFh

NOTES :

When setting to the slave device, do not transmit continuously.

Refer to 20.6.1 Access Registers Associated w ith SSU for accessing registers associated w ith SSU.

Function

Store the transmit data.

The stored transmit data is transferred to the SSTRSR register and the transmit is started

w hen detecting the SSTRSR register is empty.

When the next transmit data is w ritten to the SSTDR register during the data transmit from the

SSTRSR register, the data can be transmitted continuously.(1)

When the MLS bit in the SSMR register is set to “1” (transfer data w ith LSB-first), the data in

w hich MSB and LSB are reversed can be read, after w riting to the SSTDR register.

b7 b6 b5 b4 b3 b2 b1

SS Receive Data Register

(2)

Symbol

Address

After Reset

SSRDR

00BFh

FFh

NOTES :

2. Refer to 20.6.1 Access Registers Associated w ith SSU for accessing registers associated w ith SSU.

b7 b6 b5 b4 b3 b2 b1 b0

The SSRDR register maintains the receive data before the overrun error occurs w hen the ORER bit in the SSSR

therefore, should be discarded.

Store the receive data.(1)

The receive data is transferred to the SSRDR register and the receive operation is completed

w hen receiving 1-byte data to the SSTRSR register. At this time, the follow ing receive is

possible. The continuous receive is possible by the SSTRSR and SSRDR registers.

Function

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