R8CSLASH15 datasheet(158/277 Pages) RENESAS

158 / 277 page

R8C/14 Group, R8C/15 Group

15. Clock Synchronous Serial I/O with Chip Select (SSU)

Rev.2.10

Jan 19, 2006

Page 146 of 253

REJ09B0164-0210

Figure 15.6

SSSR Register

SS Status Register

(7)

Symbol

Address

After Reset

SSSR

00BCh

00h

Bit Symbol

Bit Name

Function

NOTES :

from “L” to “H” during transfer, the CE bit is set to “1”.

Indicates overrun error occurs and receive completes by error w hen receive. When the next serial data receive is

completed w hile the RDRF bit is set to “1” (data in the SSRDR register), the ORER bit is set to “1”. After the ORER bit

is set to “1” (overrun error occurs), do not transmit or receive w hile the ORER bit is set to “1”.

When the serial communication is started w hile the SSUMS bit in the SSMR2 register is set to “1” (four-w ire

bus communication mode) and the MSS bit in the SSCRH register is set to “1” (operates as master

device), the CE bit is set to “1” if “L” is applied to the SCS

_____

pin input. When the SSUMS bit in the SSMR2

(operates as slave device) is set to “0” (operates as slave device) and the SCS

_____

pin input changes the level

—

Refer to 20.6.1 Access Registers Associated w ith SSU for accessing registers associated w ith SSU.

The TEND and TDRE bits are set to “0” w hen w riting the data to the SSTDR register.

Overrun Error Flag(1)

0 : No overrun error occurs

1 : Overrun error occurs(3)

The TDRE bit is set to “1” w hen setting the TE bit in the SSER register to “0” (disables transmit).

TEND

Transmit End(1, 5)

0 : The TDRE bit is set to “0” w hen transmitting

the end of the bit in transmit data

1 : The TDRE bit is set to “1” w hen transmitting

the end of the bit in transmit data

ORER

—

(b4-b3)

—

Conflict Error Flag(1)

0 : No conflict error occurs

1 : Conflict error occurs(2)

RDRF

Receive Data Register Full(1, 4)

—

(b1)

Nothing is assigned. When w rite, set to “0”.

When read, its content is “0”.

0 : No data in SSRDR register

1 : Data in SSRDR register

b3 b2 b1

b7 b6 b5 b4

When reading “1” and w riting “0”, the CE, ORER, RDRF, TEND and TDRE bits are set to “0”.

The RDRF bit is set to “0” w hen reading out the data from the SSRDR register.

Nothing is assigned. When w rite, set to “0”.

When read, its content is “0”.

TDRE

Transmit Data Empty(1, 5, 6)

0 : Data is not transferred from the SSTDR

to SSTRSR registers

1 : Data is transferred from the SSTDR to

SSTRSR registers

R8C/15 Datasheet(PDF) 158 Page - Renesas Technology Corp

R8C/15 Datasheet(HTML) 158 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL