R8CSLASH15 datasheet(154/277 Pages) RENESAS

154 / 277 page

R8C/14 Group, R8C/15 Group

15. Clock Synchronous Serial I/O with Chip Select (SSU)

Rev.2.10

Jan 19, 2006

Page 142 of 253

REJ09B0164-0210

Figure 15.2

SSCRH Register

SS Control Register H

(4)

Symbol

Address

After Reset

SSCRH

00B8h

00h

Bit Symbol

Bit Name

Function

NOTES :

The RSSTP bit is disabled w hen the MSS bit is set to “0” (operates as slave device).

b7 b6 b5 b4 b3 b2 b1 b0

—

(b4-b3)

—

Nothing is assigned. When w rite, set to “0”.

When read, its content is “0”.

Master/Slave Device Select Bit(2)

0 : Operates as slave device

1 : Operates as master device

MSS

CKS1

CKS2

Transfer Clock Rate Select Bit(1)

b2 b1 b0

0 0 0 : f1/256

0 0 1 : f1/128

0 1 0 : f1/64

0 1 1 : f1/32

1 0 0 : f1/16

1 0 1 : f1/8

1 1 0 : f1/4

1 1 1 : Do not set

CKS0

Refer to 20.6.1 Access Registers Associated w ith SSU for accessing registers associated w ith SSU.

The SSCK pin functions as the transfer clock output pin w hen the MSS bit is set to “1” (operates as master device).

The MSS bit is set to “0” (operates as slave device) w hen the CE bit in the SSSR register is set to “1” (conflict error

occurs).

RSSTP

Receive Single Stop Bit(3)

0 : Maintains receive operation after

receiving 1-byte data

1 : Completes receive operation after

receiving 1-byte data

—

(b7)

Nothing is assigned. When w rite, set to “0”.

When read, its content is “0”.

The set clock is used w hen the internal clock is selected.

—

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