R8CSLASH15 datasheet(157/277 Pages) RENESAS

157 / 277 page

R8C/14 Group, R8C/15 Group

15. Clock Synchronous Serial I/O with Chip Select (SSU)

Rev.2.10

Jan 19, 2006

Page 145 of 253

REJ09B0164-0210

Figure 15.5

SSER Register

SS Enable Register

(1)

Symbol

Address

After Reset

SSER

00BBh

00h

Bit Symbol

Bit Name

Function

NOTES :

b3 b2 b1

b7 b6 b5 b4

CEIE

—

Conflict Error Interrupt Enable Bit 0 : Disables conflict error interrupt request

1 : Enables conflict error interrupt request

—

(b2-b1)

Nothing is assigned. When w rite, set to “0”.

When read, its content is “0”.

0 : Disables transmit data empty interrupt

request

1 : Enables transmit data empty interrupt

request

0 : Disables transmit end interrupt request

1 : Enables transmit end interrupt request

TEIE

Transmit End Interrupt Enable Bit

RIE

Refer to 20.6.1 Access Registers Associated w ith SSU for accessing registers associated w ith SSU.

Receive Enable Bit

0 : Disables receive

1 : Enables receive

Transmit Enable Bit

0 : Disables transmit

1 : Enables transmit

0 : Disables receive data full and overrun

error interrupt request

1 : Enables receive data full and overrun

error interrupt request

Receive Interrupt Enable Bit

TIE

Transmit Interrupt Enable Bit

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