R8CSLASH15 datasheet(183/277 Pages) RENESAS

183 / 277 page

R8C/14 Group, R8C/15 Group

16. A/D Converter

Rev.2.10

Jan 19, 2006

Page 171 of 253

REJ09B0164-0210

Figure 16.3

ADCON2 and AD Registers

A/D Control Register 2

(1)

Symbol

Address

After Reset

ADCON2

00D4h

00h

Bit Symbol

Bit Name

Function

NOTES :

b3 b2 b1

Reserved Bit

Set to “0”

b7 b6 b5 b4

0 : Without sample and hold

1 : With sample and hold

If the ADCON2 register is rew ritten during A/D conversion, the conversion result is indeterminate.

SMP

A/D Conversion Method Select Bit

Nothing is assigned. When w rite, set to “0”.

When read, its content is “0”.

—

(b7-b4)

—

(b3-b1)

A/D Register

Symbol

Address

After Reset

00C1h-00C0h

Indeterminate

Function

When BITS bit in ADCON1 register is set to “1”

(10-bit mode).

When BITS bit in ADCON1 register is set to “0”

(8-bit mode).

8 low -order bits in A/D conversion result

A/D conversion result

Nothing is assigned. When w rite, set to “0”.

When read, its content is “0”.

—

2 high-order bits in A/D conversion result

When read, its content is indeterminate.

(b8)

(b15)

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